It is known that integrated circuits, in particular integrated circuits based on CMOS (Complementary Metal Oxide Semiconductor) circuit technology, must be protected against damaging electrostatic discharges. The aim in this case is to ensure that, in the case of a network of a circuit which can be electrostatically charged from the outside via a pad, electrostatic charging via a further network which is connected to the external environment can be dissipated via a low impedance to the outside again without any damage to the integrated circuit. This is done by means of ESD (Electrostatic Discharge) protective elements having appropriately broad and thus low-impedance supply buses, which are each arranged between two networks. ESD protective elements such as these fundamentally have a high impedance and form a low-impedance discharge path only in the event of ESD, that is to say when an electrostatic charge is supplied, so that it is impossible for a destructive discharge to take place via parallel-connected circuit parts. Semiconductor components, in particular diodes or thyristor structures, are typically used as ESD protective elements.
An ESD load can be simulated by the so-called HBM (Human Body Model). This is based on the assumption that an ESD load represents a high-impedance drive, that is to say a drive which forces a current to flow, for a pad.
The so-called diode ESD protective concept may be used for protection of an input or output of a monolithically integrated circuit. This concept is based on ESD protective diodes which are arranged at each input or output pad (I/O pad) of the circuit and are electrically connected not only to the respective I/O pad but also to one of the two supply networks, the so-called positive VDD network and the ground network (VSS network). When an ESD load occurs on the I/O pad, a discharge path is formed via one of the protective diodes depending on the polarity of the ESD pulse, dissipating the applied ESD charge to the VDD network or VSS network. If this VDD network or VSS network is not connected to the external environment, the respective other supply network being connected to it instead, an additional low-impedance path is also provided between the two supply networks. A further ESD protective element between the VDD network and the VSS network is used for this purpose and is also referred to as a power clamp, producing low-impedance charge equalization between the two supply networks. A power clamp such as this is frequently in the form of a thyristor structure.
One factor for the protective effect of the ESD protective concept described above is that the potential at the I/O pad is limited to non-critical values. If a specific critical magnitude of the potential at the I/O pad is exceeded, this results in a discharge via the circuit parts which are internally connected to the I/O pad. In the process, the gate oxide or diffusion layers of the I/O transistors is or are generally severally damaged or even destroyed. As semiconductor process technology becomes increasingly miniaturized, with the gate oxide thicknesses and extents of diffusion layers becoming ever smaller, the magnitude of the critical potential at an I/O pad is also decreasing. In order to ensure adequate voltage limiting in the event of ESD at the I/O pad, the power clamp can also be driven by means of a drive circuit that is set to be appropriately sensitive, and which is also referred to as a trigger circuit. The trigger circuit detects the presence of an ESD load, and triggers the power clamp in the event of ESD. In principle, there are two implementation options for the design of the trigger circuit: the trigger circuit may be designed in such a way that it detects an overvoltage between the supply networks. This can be achieved, for example, by current measurements on a diode chain. Alternatively, for example in the case of a so-called RC trigger, the transient voltage change between the supply networks can also be used for detection of an ESD load. Fundamentally, trigger circuits such as these have to take account of the fact that, in the event of an ESD load on an I/O pad, the additional diode path means that the voltage between the I/O pad and the VSS network is about 0.8–1.0 V greater than the voltage between the supply networks. The trigger threshold, that is to say the overvoltage or the transient voltage change at which the power clamp is triggered, is therefore set at an appropriately low level. Setting the trigger threshold to a low level such as this has the disadvantage that, when the integrated circuit is being operated at high temperatures, this can result in leakage currents via the trigger circuit and possibly also flowing via the power clamp, or the possibility of the power clamp being triggered inadvertently. In both situations, the functionality of the integrated circuit can be massively adversely affected: leakage currents cause an additional power loss, while inadvertent triggering results in a short circuit between the supply networks and can be rectified only with difficulty during operation of the circuit. Leakage currents frequently occur particularly when using overvoltage detection. Inadvertent triggering in the VDD network can be frequently observed. This is particularly true in the case of RC triggers, which are caused by detection of transient disturbance signals that are not ESD-dependent.
U.S. Pat. No. 5,576,557 describes an ESD protective circuit that is used for ESD protection of an input or output of a monolithically integrated circuit. The ESD protective circuit has a first and a second thyristor structure (SCR—Silicon Controlled Rectifier) that are designed as so-called low-voltage trigger SCRs (LVTSCR). An LVTSCR has an additional MOS transistor in order to trigger the thyristor. The anode and an anode-side control connection of the first thyristor structure are connected to the VDD network, while the cathode of the first thyristor structure is connected to the I/O pad to be protected, and a cathode-side control connection of the first thyristor structure is connected to the VSS network. Furthermore, the cathode and a cathode-side control connection of the second thyristor structure are connected to the VSS network, while the anode of the second thyristor structure is connected to the I/O pad to be protected and an anode-side control connection of the second thyristor structure is connected to the VDD network. This arrangement means that a total of two bipolar transistor structures which are inherent in the two thyristor structures are connected on the emitter side to the I/O pad. In the event of an ESD load on the I/O pad, one base/emitter junction of one of the two bipolar transistor structures is driven in the forward direction. The base potential change associated with this results in a drain-bulk breakdown of the LVTSCR-inherent MOS transistor. This drain-bulk breakdown results in triggering of the respective thyristor. This solution has the disadvantage that the triggering of the respective thyristor via the drain-bulk breakdown of an MOS transistor does not occur until the potential at the I/O pad has a specific magnitude, even if the magnitude of the potential is reduced further after the triggering. This specific potential magnitude is in the same order of magnitude as the breakdown voltage of the MOS transistor, that is to say 11 to 13 volts. If the potential magnitude before triggering of the thyristor is also only briefly above the critical magnitude mentioned above, damage to or destruction of the circuit which is connected to the I/O pad internally cannot be precluded despite the presence of an ESD protective circuit. The risk of ESD damage is in this case particularly high with modern semiconductor process techniques with structure sizes in the sub-0.1 micrometer range.
FIG. 1 shows an ESD protective circuit as known from the prior art for an input or output of an integrated circuit, based on the diode ESD protective concept. This has two diodes 1 and 2, which are electrically connected to an I/O pad 3 of the input and output of an internal circuit (indicated by the arrow 4), and in each case to one of the two supply networks VDD (positive potential) and VSS (ground potential). The diodes are connected such that they do not provide a conductive connection during normal operation of the integrated circuit. Furthermore, a trigger circuit 5 is connected between the supply networks VDD and VSS and identifies either the presence of an overvoltage or, alternatively, a transient voltage change between the supply networks as an indication of an ESD load. In response to the detection of an ESD load, the trigger circuit 5 drives a power clamp element 7 via a control signal 6. The control signal is used to trigger the power clamp element 7 which is connected between the supply networks, with a conductive connection being formed between the supply networks VDD and VSS when the power clamp element 7 is triggered. Furthermore, a power clamp diode 8 is also provided between the supply networks VDD and VSS.
In principle, a distinction can be drawn between four types of ESD load at an I/O pad: an ESD load at an I/O pad with a positive voltage polarity to the externally short-circuited VSS network (PS-ESD load); an ESD load at an I/O pad with a positive voltage polarity to the externally short-circuited VDD network (PD-ESD load); an ESD load at an I/O pad with a negative voltage polarity to the externally short-circuited VSS network (NS-ESD load); and an ESD load at an I/O pad with a negative voltage polarity to the externally short-circuited VDD network (ND-ESD load).
In the event of a PS-ESD load, the diode 1 becomes forward-biased, and the trigger circuit 5 identifies an ESD load on the basis of the transient voltage change or the overvoltage, and triggers the power clamp element 7 which, after triggering, produces a low-impedance connection between the supply networks VDD and VSS. In the case of an ESD load such as this, the voltage between the I/O pad and VSS network is limited to low values by the low-impedance discharge path.
In the event of a PD-ESD load, the diode 1 becomes forward-biased, so that a low-impedance discharge path is created between the I/O pad and the externally short-circuited VDD network. This limits the voltage between the I/O pad and the VDD network.
In the event of an ND-PSD load or an NS-ESD load, a low-impedance discharge path is formed in an analogous manner to that for a PS-ESD load or a PD-ESD load, with the diode 2 then being forward-biased rather than the diode 1.
The diode ESD concept illustrated in FIG. 1 is based on monitoring (monitoring of the overvoltage or the voltage change) of the voltage between the VDD network and the VSS network.